Statistics counters are used to perform data analytics in a high speed network device. To be useful, an architecture needs to store a large number of counters. Although off-chip DRAM (dynamic random access memory) can be used, it cannot accommodate high speed counter updates. On-chip SRAM (static random access memory) allows for greater speed but is very expensive. Since the memory is one of the most expensive resources in an SOC (system on chip), it is critical to efficiently and flexibly utilize the memory. When dealing with storing multiple counters, there exists a tradeoff between fewer larger counters or more smaller counters. Ideally, each counter is long enough to avoid integer overflow, the wrapping around of the counter. However, in standard practice, this leads to overprovisioning, assigning the worst case number of bits for all counters.